This invention relates generally to field-effect transistors (FET's), and more particularly, to field-effect transistors capable of operation at extremely high frequencies, as high as 300 gigahertz (GHz) or higher. Since the wavelength at these frequencies is one millimeter (mm) or less, such devices are sometimes referred to as millimeter-wave devices. High frequency transistors of this type may be usefully incorporated into monolithic circuits, either digital or analog, operating at millimeter or shorter wavelengths, or may be employed in discrete form as amplifiers or oscillators, as well as in mixers, frequency multipliers, and so forth.
By way of background, a field-effect transistor (FET) is a three-terminal amplifying or switching semiconductor device in which charge carriers flow along an active channel region between a source terminal and a drain terminal. When a bias voltage is applied to a gate terminal adjacent to the channel, a carrier depletion region is formed in the channel and the current flow is correspondingly inhibited. In a conventional FET, the source and drain terminals make contact with source and drain semiconductor regions of the same conductivity type, and the active channel takes the form of a planar layer extending between the source and drain regions. The gate terminal makes contact with the channel at a point between the source and the drain, and usually on the same face of the device as the source and drain terminals.
As indicated in the cross-referenced application, the performance of a conventional FET at high frequencies is limited principally by the transconductance of the device, as well as by the source resistance, the source inductance, and by other circuit "parasitics," or internal impedances associated with the transistor. As also discussed in the cross-referenced application, various attempts have been made to reduce parasitic impedances. Patents of interest in this regard are Decker (U.S. Pat. No. 4,141,021), Cho (U.S. Pat. No. 4,249,190), Tantraporn (U.S. Pat. No. 4,129,879), Cho et al. (U.S. Pat. No. 4,236,166), and Nelson (U.S. Pat. No. 2,985,805).
All of these prior art devices are still limited in their performance at high frequencies by a relatively low incremental transconductance per unit width, and by the presence of significant parasitic impedances. In the cross-referenced application a novel FET structure was disclosed and claimed, in which the source and gate are located on opposite faces of the semiconductor channel region, the source having an effective length substantially less than that of the gate, and being located symmetrically with respect to the gate. Two separate drains are located at opposite ends of the channel region, and current flows in two parallel paths from the source to the two drains. In this parallel configuration, the incremental transconductance per unit width is approximately twice that of a single conventional FET of similar design, thus improving the high-frequency performance of the device. The opposed gate-source configuration permits the source to be connected to a metalized ground plane. This arrangement practically eliminates source resistance and source inductance, which also improves high-frequency performance.
Although the FET structure and related method descibed in the cross-referenced application is generally satisfactory in most respects, if the dimensions of the device are reduced to achieve higher frequencies it becomes increasingly difficult to align the source and gate with the requisite accuracy. In the prior application, the source is formed as a buried region, from the same face of the substrate as the one on which the gate and drains are formed. The channel region is formed over the source region, and contact with the source is made by forming an opening in the opposite face of the substrate. Regardless of the specific structure of the device, if the source and gate are disposed on opposite faces of the substrate, there will be a significant difficulty, which will be aggravated at higher frequencies, in aligning the source and gate. The present invention is directed to a technique for alleviating this difficulty.